The demand for low cost, small size, and more functionality has become the main driving force in the electronic industry. To achieve such goals, advanced packaging techniques like flip chip, chip scale package, wafer level packaging, and 3D packages have been developed. The 3D packaging technique is developed to integrate dies, packages and passive components into one package, in other words, to achieve system in a package solution. The integration can be made in side-by-side, stacked, or both manners. The outstanding advantages of 3D package are small footprint, high performance and low cost.
FIGS. 1 to 3 are schematic flow diagrams showing the process for manufacturing a conventional stacked package structure. In the fabrication of a conventional stacked package structure 250, a chip package structure 100 is firstly provided typically, in which the chip package structure 100 is generally a chip scale package (CSP). The chip package structure 100 mainly includes a substrate 102, a chip 104, an encapsulant 108 and bumps 110, such as shown in FIG. 1. The chip 104 is attached on a top surface 112 of the substrate 102, and is electrically connected to pads (not shown) of the substrate 102 by wires 106. The encapsulant 108 is formed on the top surface 112 of the substrate 102 and fully covers the chip 104, the wires 106 and the top surface 112 of the substrate 102. The bumps 110 are set on the outer portion of a bottom surface 114 of the substrate 102, in which the bumps 110 are electrically connected to the chip 104.
Next, another chip package structure 200 is provided, in which the chip package structure 200 is mainly composed of a substrate 202, a chip 204, an encapsulant 208 and bumps 210, such as shown in FIG. 2. The chip 204 is attached on a top surface 212 of the substrate 202, and is electrically connected to pads (not shown) of the substrate 202 by wires 206. The encapsulant 208 is formed on a portion of the top surface 212 of the substrate 202 and fully covers the chip 204 and the wires 206. The bumps 210 are set on a bottom surface 214 of the substrate 202, in which the bumps 210 are electrically connected to the chip 204. The top surface 212 of the substrate 202 of the chip package structure 200 further includes a plurality of connection pads 216 deposed thereon, in which the locations of the connection pads 216 are corresponding to that of the bumps 110 on the bottom surface 114 of the substrate 102.
Then, the chip package structure 100 is stacked on the chip package structure 200, and the bumps 110 of the chip package structure 100 are respectively connected to the corresponding connection pads 216. Subsequently, a reflow step is performed, so as to connect the bumps 110 of the chip package structure 100 to the connection pads 216 of the chip package structure 200 to complete the stacked package structure 250.
However, in the connection treatment of the chip package structure 100 and the chip package structure 200, warpage will occur in the chip package structure 100 and the chip package structure 200, especially the chip package structure 100. Furthermore, the room between the substrate 102 of the chip package structure 100 and the substrate 202 of the chip package structure 200 is still large, and the connection locations between the chip package structure 100 and the chip package structure 200 are at the outer region, so that a cold joint occurs between the chip package structure 100 and the chip package structure 200. As a result, the reliability of the stacked package structure is seriously deteriorated, the yield of the package process is greatly reduced, and the cost is substantially increased.